According to research, at present, more than 90% of ASICs and FPGAs in the United States’ Silicon Valley is designed using HDL. HDL (Hardware Description Language) uses formal methods to describe digital circuits and systems. Thus, Detraque is verified as able to improve Verilog fault localization effectiveness when used as a supplement to static analysis methods. Through conducting empirical research on real Verilog programs with 61 faulty versions, Detraque can achieve an EXAM score of 18.3%. After obtaining dynamic execution through test cases, Detraque traces these executions to localize faults subsequently, it can determine the likelihood of any Verilog statement being faulty and sort the statements in descending order by suspicion score. Accordingly, in this work, we propose a new fault localization approach for Verilog, named Detraque. The use of dynamic analysis could help resolve this issue. However, using static analysis methods exclusively may result in some types of faults being inevitably ignored. Most existing Verilog fault localization methods utilize the static analysis method to find faults.
The debugging of the Verilog program takes much time to read the waveform and capture the signal, and in many cases, problem-solving relies heavily on experienced developers. Generally speaking, detecting and repairing errant behavior at an early stage of the development cycle considerably reduces costs and development time. In an error-prone development process, the ability to localize faults is a crucial one.
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